Method for bonding and debonding films using a high-temperature polymer

ABSTRACT

The invention relates to a semiconductor structure that is formed by delaminating a semiconductor substrate and by bonding the top section of the substrate to a transfer substrate. Delaminating is carried out by causing a polymer film to achieve greater adhesion that an embrittlement layer in the semiconductor substrate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] An embodiment of the present invention relates generally tointegrated circuit fabrication. More particularly, an embodiment of thepresent invention relates to debonding a thin semiconductor layer andbonding it to a transfer substrate.

[0003] 2. Description of Related Art

[0004] Thin semiconductor layers (sometimes referred to as epitaxial(EPI) wafers) are used to control the detrimental effects ofresistance-capacitance (RC) that occur in semiconductor devices. Onechallenge with thin semiconductor layers is their high cost. To thatend, one solution has been to debond a semiconductive layer from itsformerly integral substrate and to bond it to another substrate thatprovides an RC advantage over the prior art. A high-cost, and highyield-loss disadvantage is the processing needed to get a smooth enoughsurface from the debonded semiconductive layer to allow for efficientbonding to another semiconductive structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In order to more clearly depict the manner in which embodimentsof the present invention are obtained, a more particular description ofthe invention briefly described above will be rendered by reference tospecific embodiments thereof which are illustrated in the appendeddrawings. Understanding that these drawings depict only typicalembodiments of the invention that are not necessarily drawn to scale andare not therefore to be considered to be limiting of its scope, theinvention will be described and explained with additional specificityand detail through the use of the accompanying drawings in which:

[0006]FIG. 1 is an elevational cross-section of a semiconductorstructure that reveals process integration that is near back-end-of-line(BEOL) according to an embodiment;

[0007]FIG. 2 is an elevational cross-section of the semiconductorstructure depicted in FIG. 1 after formation of an embrittlement zone;

[0008]FIG. 3 is an elevational cross-section of the semiconductorstructure depicted in FIG. 2 after further processing;

[0009]FIG. 4 is an elevational cross-section of the semiconductorstructure depicted in FIG. 3 after further processing;

[0010]FIG. 5 is an elevational cross-section of the semiconductorstructure depicted in FIG. 4 after further processing;

[0011]FIG. 6 is an elevational cross-section of the semiconductorstructure depicted in FIG. 5 after further processing;

[0012]FIG. 7 is an elevational cross-section of the semiconductorstructure depicted in FIG. 6 after further processing;

[0013]FIG. 8 is an elevational cross-section of the semiconductorstructure depicted in FIG. 7 after further processing;

[0014]FIG. 9 is a chart that describes a process flow embodiment; and

[0015]FIG. 10 is an elevational cross-section of a multi-layersemiconductor structure according to an embodiment.

DETAILED DESCRIPTION OF THE INVENTION

[0016] The present invention relates to a process of forming a substratesuch as a semiconductor substrate. In a general embodiment, an activelayer of a substrate is fractured away from the substrate by adhesion toa polymer film. A stiffener, that is disposed over the active layer,prevents the active layer from shattering.

[0017] Polymers

[0018] The polymer material is preferably a material that will withstandmedium-range processing temperatures such as from about 100° C. to about450° C. Additionally, the polymer material has a low moisture orvolatile-matter content such that temperature cycling through thismedium range causes the polymer material to emit insufficient amounts ofgas that would otherwise delaminate the polymer film from the stiffener.

[0019] In one embodiment, the polymer has a glass transition temperatureabove about 300° C. to about 450° C. The upper limit is determined bythe thermal stability of the polymer. The polymer may be applied by aspin-bake-cure processing technique known in the art. The polymer mayalso have a minimal out-gassing behavior during thermal processing.

[0020] Various polymers may be selected. One group of polymers includesarylene ether polymers, such as poly(arylene ether) (PAE), poly(aryleneether ether ketone) (PAEEK), poly(arylene ether ether acetylene)(PAEEA), poly(arylene ether ether acetylene ether ether ketone)(PAEEAEEK), poly(arylene ether ether acetylene ketone) (PAEEAK), andpoly(naphthylene ether) (PNE). Such polymers include but are not limitedto homopolymers, block or random copolymers, graft copolymers, polymerblends, interpenetrating polymer networks (IPNs), andsemi-interpenetrating polymer networks (SIPNs).

[0021] The polymers are dissolved in a solvent according to knowntechnique. Various solvents are known in the art. For example, solventshave been used for photoresist materials and for organic interlayerdielectric (ILD) materials. Solvents include alcohols, ketones, ethers,and combinations thereof. Examples of alcoholic solvents includemethanol, ethanol, propanol, isopropanol, butanol, methyl cellosolve,cellosolve, butyl cellosolve, and the like. Examples of ketone solventsinclude methyl ethyl ketone, methyl isobutyl ketone, cyclopentanone,cyclohexanone, cycloheptanone, cyclooctanone, γ-butyrolactone,N-methylpyrrolidinone, N-cyclohexylpyrrolidinone andN,N-dimethylacetamide. Examples of ether solvents include aliphatic,aromatic, and aromatic aliphatic ethers. Examples of ethers includemethyl ether, ethyl ether, n-propyl ether, isopropyl ether, n-butylether, vinyl ether, allyl ether, anisole, methyl anisole, phenetole(ethyl phenyl ether), phenyl ether,1,4-dioxane, tetrahydrofuran,isopropyl phenyl ether, and the like.

[0022] Because an embodiment of the present invention contemplates useof the polymers at temperatures in the range around 400° C., ethers withhigher boiling points may be selected. Examples thereof include, but arenot limited to n-butyl ether (B.p. 142° C.), anisole (B.p. 154° C.),phenetole (B.p. 172° C.), phenyl ether (B.p. 259° C.), 1,4 dioxane (B.p.101° C.), and the like.

[0023] Processing

[0024] The following description includes terms, such as upper, lower,first, second, etc. that are used for descriptive purposes only and arenot to be construed as limiting. The embodiments of an apparatus orarticle of the present invention described herein can be manufactured,used, or shipped in a number of positions and orientations.

[0025] Reference will now be made to the drawings wherein likestructures will be provided with like reference designations. In orderto show the structures of embodiments of the present invention mostclearly, the drawings included herein are diagrammatic representationsof integrated circuit structures. Thus, the actual appearance of thefabricated structures, for example in a photomicrograph, may appeardifferent while still incorporating the essential structures ofembodiments of the present invention. Moreover, the drawings show onlythe structures necessary to understand embodiments of the presentinvention. Additional structures known in the art have not been includedto maintain the clarity of the drawings.

[0026]FIG. 1 is an elevational cross-section of a semiconductorstructure 10 during processing. According to an embodiment,front-end-of-line (FEOL) processing is substantially completed, andmetallization and other back-end-of-line (BEOL) processing has not beeninitiated. A gate 12 is represented as being disposed upon an uppersurface 14 of a first substrate 16. First substrate 16 may be understoodto be a singulated die from a wafer, or it may be an unsingulatedsection of a wafer.

[0027]FIG. 2 illustrates further processing, wherein first substrate 16has been ion implanted to a certain depth below upper surface 14 to forman embrittlement zone 18. Embrittlement zone 18 may be formed by one ofseveral techniques, such as SmartCut® by Soitec USA, Inc. of Peabody,Mass., or the cleaving process of Silicon Genesis Corporation ofCampbell, Calif., or the ELTRAN® (Epitaxial Layer TRANsfer) process ofCanon, USA, Santa Clara, Calif.

[0028] The formation of embrittlement zone 18 acts to further definefirst substrate 16 into a top section 20 and a bottom section 22. Topsection 20 may also be referred to as a first active substrate 20.Embrittlement zone 18 is processed under conditions that it will notcause bottom section 22 to delaminate until subsequent processing. Afterthe formation of embrittlement zone 18, further processing is carriedout. A stiffener 24 is formed over upper surface 14 in a manner thatengulfs gate 12 without causing detrimental change thereto. In oneembodiment, stiffener 24 is formed by chemical vapor deposition (CVD)such as the decomposition of tetra ethyl ortho silicate (TEOS) underprocessing conditions that do not exceed about 200° C. Other processesmay be selected, but it is preferable to form stiffener 24 at as low atemperature as feasible, or at least low enough to prevent prematuredelamination of bottom section 22. It is noted that gate 14 extends intostiffener 24.

[0029]FIG. 3 illustrates further processing. As noted by the neworientation of gate 12 first substrate 16 has been inverted (forillustrative purposes) with respect to FIGS. 1 and 2. A polymer film 26is formed on a second substrate 28. As set forth herein, polymer film 26is formed according to processing parameters in this disclosure, andaccording to known technique. FIG. 3 represents the bonding of stiffener24 with polymer film 26 as they are joined. In one embodiment, stiffener24 has a thickness in a range from about 0.5 microns to about 10microns. In another embodiment, stiffener 24 has a thickness in a rangefrom about 1 of about 1 micron to about 4 microns. In one embodiment,polymer film 26 has a thickness in a range from about 200 nm to about1,000 nm. In another embodiment, polymer film 26 has a thickness in arange from about 360 nm to about 750 nm.

[0030] It is noted that second substrate 28 has a plurality of back-siderecesses 30 that are provided for optional subsequent removal of polymerfilm 26 as set forth herein. During further processing while polymerfilm 26 and embrittlement zone 18 are contemporary structures, a firstdelamination stress exists in embrittlement zone 18, that during thermalprocessing up to about 450° C., is greater that a second delaminationstress that exists within the area of polymer film 26 disposed betweensecond substrate 28 and stiffener 24.

[0031] As depicted in FIG. 4, second substrate 28 is bonded with firstsubstrate 16 by the adhesive quality of polymer film 26 to stiffener 24.Stiffener 24 is typically not planarized by any process prior to thebonding of second substrate 28 to first substrate 16. Accordingly,stiffener 24 may have a surface roughness that is greater than theminimum that was previous required where two oxide layers were bonded.In one embodiment, stiffener 24 has a microsurface roughness that isgreater than or equal to about 10 nm. In one embodiment, stiffener 24has a microsurface roughness that is greater than or equal to aboutprime grade polish as is quantitatively understood in the art.Accordingly, processing is expedited where no previous surfacepreparation of stiffener 24 is required. Further processing is carriedout where semiconductor structure 10 is heated under conditions to causestress in embrittlement zone 18 to increase until bottom section 22delaminates from top section 20. Heating is carried out to a temperaturebetween room temperature and about 450° C. In one embodiment, heating iscarried out in a temperature range from about 200° C. to about 400° C.

[0032] The presence of polymer film 26 has at least two qualities.First, because polymer film 26 has adhesive strength during heating thatsurpasses the adhesive attraction between top section 20 of firstsubstrate 16 and bottom section 22. Second, because polymer film 26 issoft, it flows into the rough topology of stiffener 24; no planarizingof stiffener 24 is required. On the other hand, stiffener 24 is providedfor various reasons. Because polymer film 16 is soft relative to topsection 20 of first substrate 16, and because top section 20 may beextremely brittle, stiffener 24 acts to prevent top section 20 fromshattering during the delamination of bottom section 22. Additionally,stiffener 24 acts as a BEOL interlayer dielectric layer duringmetallization and other processing.

[0033] As depicted in FIG. 4, bottom section 22 has delaminated from therest of semiconductor structure 10 and a fracture surface 32 of topsection 20 is exposed. In one embodiment, top section 20 has a thicknessin a range from about 200 nm to about 800 nm. In another embodiment, topsection 20 has a thickness in a range from about 300 nm to about 500 nm.In another embodiment, top section 20 has a thickness of about 360.

[0034] In another embodiment, it is noted that the semiconductorstructure depicted in FIG. 4 comprises a novel silicon-on-polymer (SOP)insulated device. Where polymer film 26 has sufficient dielectricproperties, it may act as an isolation dielectric. One such polymer isFLARE® made by AlliedSignal Inc. of Morristown, N.J.

[0035] Semiconductor structure 10 is depicted in FIG. 5, after furtherprocessing. After the delamination of bottom section 22 (FIG. 4), topsection 20, as the remnant of first substrate 16 (FIGS. 1-4), has afirst dielectric layer 34 formed on the fracture surface 32 of topsection 20. In one embodiment, first dielectric layer 34 is an oxidesuch as a thermal oxide or a CVD oxide. In one embodiment, firstdielectric layer 34 is a nitride such as a thermal nitride or a CVDnitride. In one embodiment, first dielectric layer 34 is a carbide suchas a CVD carbide. In one embodiment, first dielectric layer 34 is acarbon-doped oxide (CDO) such as a carbon-doped (implanted) thermaloxide or a CVD CDO. Additionally, combinations thereof may be used.

[0036] In one embodiment, first dielectric layer 34 is formed by CVD ata temperature below the glass transition temperature of polymer film 26.CVD processing is also carried out under conditions that act to form assmooth a surface of first dielectric layer 34 as possible. In oneembodiment, first dielectric layer 34 is made of silica, SiO₂, that isformed by CVD in a temperature range from about 100° C. to about 200° C.Other oxides may be used for first dielectric layer 34 including oxidessuch as alumina, ceria, thoria, zirconia, hafnia, titania, andcombinations thereof. Nitrides may be made such as aluminum nitride,cerium nitride, thorium nitride, zirconium nitride, hafnium nitride,titanium nitride, and combinations thereof.

[0037] In one alternative embodiment, a planarization process flow isfollowed to smooth first oxide layer 34. Planarization may be done bymechanical polishing (MP), chemical etchback, chemical-mechanicalpolishing (CMP), and combinations thereof.

[0038]FIG. 6 illustrates further processing. After the formation offirst dielectric layer 34, semiconductor structure 10 is inverted (forillustrative purposes), and a third substrate 36 with a third substratedielectric layer 38 is brought into contact with first dielectric layer34. In one embodiment, third substrate dielectric layer 38 is an oxidesuch as a thermal oxide or a CVD oxide. In one embodiment, thirdsubstrate dielectric layer 38 is a nitride such as a thermal nitride ora CVD nitride. In one embodiment, third substrate dielectric layer 38 isa carbide such as a CVD carbide. In one embodiment, third substratedielectric layer 38 is a carbon-doped oxide (CDO) such as a carbon-doped(implanted) thermal oxide or a CVD CDO. Additionally, combinationsthereof may be used.

[0039] Third substrate may be referred to herein as the final transfersubstrate or simply the transfer substrate. In one embodiment, thirdsubstrate dielectric layer 38 and first dielectric layer 34 aresubstantially identical to each other. By “substantially identical”, itis understood that the two dielectric layers may be made by the sameprocess such as CVD or thermal growth. Similarly, the two dielectriclayers may be made of the same dielectric compound. Similarly, the twodielectric layers may vary from each other in composition and textureunder ordinary process parameter fluctuations, or they may vary fromeach other due to the substrate onto which they are deposited.Similarly, first dielectric layer 34 and third substrate dielectriclayer 38 may be formed by a thermal dielectric growth, CVD, and acombination thereof.

[0040] The bond between first dielectric layer 34 and third substratedielectric layer 38 typically forms at room temperature, whereinordinary hydrogen bonding between the dielectric surfaces occurs.Processing may be done to strengthen the bond, including heating thesemiconductor structure 10 up to about 450° C. In one embodiment, thetwo dielectric layers are oxides. During such heating (and duringsubsequent BEOL heating if any), the hydrogen bonds between firstdielectric layer 34 and third substrate dielectric layer 38 aregradually replaced by oxide bonds, for example SiO₂ bonds.

[0041] After the formation of the composite depicted in FIG. 6, furtherprocessing is carried out to delaminate second substrate 28 at polymerfilm 26. Processing is carried out to attenuate the strength of polymerfilm 26. FIG. 7 illustrates this process flow. In one embodiment, a wetetch is carried out that dissolves polymer film 26. In anotherembodiment, an oxygen plasma etch is carried out. In one embodiment,lateral access etching is done that begins to form lateral recesses 40that attenuate polymer film 26. In another embodiment, backside-accessrecesses 42 begin to form that attenuate polymer film. It should beunderstood by one of ordinary skill in the art that a combination ofetches may be carried out with a combination of accesses to polymer film26. In another embodiment, polymer film 26 is heated to itsdecomposition point, while the bond between first oxide layer 34 andthird substrate oxide layer 38 continues to strengthen. Such processingmay be in the temperature range from about 200° C. to about 800° C. orhigher.

[0042] After sufficient attenuation of polymer film 26, second substrate28 delaminates and stiffener 24 is exposed as depicted in FIG. 8.Thereafter, further BEOL processing such as metallization may be done.

[0043] The following is a process experiment. Reference may be made toFIGS. 1-8. A 200-mm silicon wafer was implanted with hydrogen ions at adose of about 5×10¹⁶ cm⁻² and an energy of about 30 keV through a100-nm, thermally grown silicon oxide layer (not pictured). Layers ofplasma-enhanced TEOS were deposited as the stiffener 24 on the wafer 16at a temperature of about 350° C. The thickness of the TEOS layers thatmade up stiffener 24 ranged from about one to about five microns. Aseparate silicon wafer (the so-called handle wafer), as a secondsubstrate 28 were coated with a PAE spin-on polymer. The polymerthickness ranged from about 400 nm to about 750 nm. The implanted waferwas cleaned in SC1 (ammonium hydroxide:peroxide:deionized water 1:1:5)at about 75° C., rinsed in deionized water, and bonded to secondsubstrate 28 at room temperature. The bonded semiconductor structure 10was annealed in an oven at about 300° C. for about 30 minutes tostrengthen the bonding, and then at about 400° C. for about one hour tofracture the implanted first substrate 16 along embrittlement zone 18. Ascanning electron microscope (SEM) analysis indicated a top section 20of about 360 nm thick disposed against an about 1 micron-thick stiffener24, in turn disposed against the polymer film 26, which similarly isdisposed on second substrate 28. After debonding along embrittlementzone 18, dissolution was carried out through back-side recesses 30.Back-side recesses were set on a 2 mm square pitch.

[0044] In a second experiment, all conditions of the first experimentwere repeated with the variation that stiffener was about 4 micronsthick.

[0045] The following is a process example according to an embodiment.Reference may be made to FIGS. 1-8. A 200-mm first substrate 16 isprovided with process integration (represented by gate 12) disposed uponupper surface 14. Ion implantation is carried out according to knowntechnique until an embrittlement zone 18 has been formed that definesthe top section 20 and the bottom section 22 of first substrate 16.

[0046] After the formation of embrittlement zone 18 a CVD process iscarried out during which TEOS is decomposed at a temperature of about200° C. to form stiffener 24. Stiffener has a microsurface roughnessgreater than or equal to about 10 nm. Processing continues by providinga second substrate 28. A polymer film 26 is formed on second substrate28. The polymer that is selected is applied by a spin-bake-cureprocessing technique known in the art. The arylene ether, PAE isdissolved in an aliphatic aromatic ether solvent and spun onto secondsubstrate 28. A spin-on process is carried out by depositing thePAE-solvent solution as a fluid in a puddle prime onto second substrate28 for a period of from about 5 to 25 seconds and rotating secondsubstrate 28 in a rotational range from about 300 revolutions per minute(rpm) to about 6000 rpm and for a time range from about 5 seconds toabout 20 seconds. Polymer film 26 is then cured according to knowntechnique.

[0047] After the formation of polymer film 26 on second substrate 28,polymer film 26 and stiffener 24 are joined by pressing and optionalthermal cycling that causes polymer film 26 to adhere thereto. Thermalprocessing continues by elevating the temperature within embrittlementzone 18 until the delamination stress causes bottom section 22 to spalloff.

[0048] Thereafter, a first dielectric layer 34 is formed by CVD of TEOSonto the fracture surface 32 of top section 20. First dielectric layer34 is optionally planarized by CMP until it has a roughness that isabout less than or about equal to prime grade polish as is known in theart. A third substrate 36 is prepared with an SiO₂ layer that issubstantially identical material to first oxide layer 34. Thereafter,first dielectric layer 34 and the third substrate dielectric layer 38are joined.

[0049] An oxygen plasma etch is next followed that attenuates polymerfilm 26. Access to polymer film 26 is achieved to form a lateral recess40 until second substrate second substrate 28 delaminates.

[0050] In another process example, all processing is the same as in thefirst example with the difference that backside-recess 30 etching 42 iscarried out. In a third process example, all processing is the same asin the first example with the addition of backside-recess 30 etching 42.

[0051]FIG. 9 illustrates a process embodiment of the present invention.According to an embodiment, a stiffener is formed 900 upon a firstsubstrate that includes a top section and a bottom section delineated byan embrittlement zone. Next, the stiffener is contacted 910 with apolymer film that is disposed upon a second substrate. After contactingthe polymer film against the stiffener, the bottom section isdelaminated 920. A third substrate is brought into contact 930 with thetop section of the first substrate, and the polymer film is attenuated.After sufficient attenuation, the second substrate delaminates 940.

[0052] In one embodiment, it is understood that first substrate 16,after bottom section 22 has delaminated, is likely able to sustain a newprocess flow that creates a new embrittlement zone and a new top- andbottom section that can be debonded as set forth herein. In this way,first substrate 16 may be used through several cycles as a “universal”first substrate.

[0053] In another embodiment, the process of building a multi-levelmicroelectronic device is carried out as depicted in part in FIG. 10.With reference to FIG. 8, it is noted that stiffener 24, when freed fromsecond substrate 28, is a dielectric surface that may be characterizedas a similar dielectric surface as third substrate dielectric layer 38as seen in FIG. 6. Accordingly the bonded, bottom silicon-film device44, depicted in FIG. 10 is an analogous structure to third substrate 36and third substrate dielectric layer 38 prior to the reception of astructure such as that depicted in FIG. 5.

[0054] According to this embodiment, a multi-level semiconductorstructure 110 is being processed that includes the bonded, bottomsilicon-film device 44 and a bonded, upper silicon-film device 46.Accordingly, it is understood that bonded, upper silicon-film device 46may have more than one similar device disposed below it. Structures aresimilar in bonded, upper silicon-film device 46 including an uppersection 120, a stiffener 124, a polymer film 126, a first oxide layer134, etc.

[0055] It will be readily understood to those skilled in the art thatvarious other changes in the details, material, and arrangements of theparts and method stages which have been described and illustrated inorder to explain the nature of this invention may be made withoutdeparting from the principles and scope of the invention as expressed inthe subjoined claims.

What is claimed is:
 1. A process comprising: forming a stiffener upon afirst substrate, wherein the first substrate includes a top section anda bottom section, wherein the stiffener is disposed against the topsection; contacting the stiffener with a polymer film that is disposedupon a second substrate; and delaminating the bottom section.
 2. Theprocess according to claim 1, wherein contacting the stiffener with apolymer film includes: forming the polymer film on the second substrate;and contacting the polymer film against the stiffener under conditionsto cause a greater adhesion force between the polymer film and thestiffener than between the top section and the bottom section.
 3. Theprocess according to claim 1, wherein forming a stiffener includes:depositing an oxide on the top section of the first substrate, whereinthe stiffener has a roughness that greater than or equal to prime gradepolish.
 4. The process according to claim 1, wherein delaminating thebottom section includes: forming an embrittlement zone in the substrateto form the top section and the bottom section; and heating underconditions to separate the bottom section from the top section.
 5. Theprocess according to claim 1, wherein delaminating the bottom sectionincludes: forming an embrittlement zone in the substrate to form the topsection and the bottom section; and heating under conditions to separatethe bottom section from the top section.
 6. The process according toclaim 1, further including: contacting the top section with a thirdsubstrate; and delaminating the second substrate.
 7. The processaccording to claim 1, further including: contacting the top section witha third substrate; and delaminating the second substrate, whereindelaminating the second substrate includes attenuating the polymer film,selected from back-side access through the second substrate and lateralaccess between the second substrate and the third substrate, and thecombination thereof.
 8. The process according to claim 1, whereindelaminating the bottom section exposes a fracture surface, furtherincluding: forming a first dielectric layer upon the fracture surface;contacting the fracture surface with a dielectric layer on a thirdsubstrate; and delaminating the second substrate.
 9. The processaccording to claim 1, wherein delaminating the bottom section exposes afracture surface, further including: forming a first dielectric layerupon the fracture surface; contacting the top section underside with adielectric layer on a third substrate; and delaminating the secondsubstrate, wherein delaminating the second substrate includesattenuating the polymer film, selected from back-side access through thesecond substrate and lateral access between the second substrate and thethird substrate, and the combination thereof.
 10. A process of forming abonded epitaxial film device comprising: forming an active device upon atop section of a first substrate; forming a stiffener upon the topsection of the first substrate, wherein the first substrate includes abottom section; contacting the stiffener with a polymer film that isdisposed upon a second substrate; delaminating the bottom section fromthe top section along a fracture surface; forming a first dielectriclayer upon the fracture surface; contacting the first dielectric layerwith a dielectric layer on a third substrate; and delaminating thesecond substrate.
 11. The process according to claim 10, after formingan active device and before forming a stiffener, further including:defining the top section from the bottom section by forming anembrittlement zone therebetween.
 12. The process according to claim 10,after forming an active device and before forming a stiffener, furtherincluding: implanting ions into the substrate to form an embrittlementzone and thereby defining the top section from the bottom section. 13.The process according to claim 10, before contacting the stiffener witha polymer film, further including: forming a polymer film on the secondsubstrate, wherein the polymer film is selected from poly(arylene ether)(PAE), poly(arylene ether ether ketone) (PAEEK), poly(arylene etherether acetylene) (PAEEA), poly(arylene ether ether acetylene ether etherketone) (PAEEAEEK), poly(arylene ether ether acetylene ketone) (PAEEAK),poly(naphthylene ether) (PNE), and combinations thereof.
 14. The processaccording to claim 10, before contacting the stiffener with a polymerfilm, further including: forming a polymer film on the second substrate,wherein the polymer film is selected from homopolymers, blockcopolymers, graft copolymers, polymer blends, interpenetrating polymernetworks (IPNs), and semi-interpenetrating polymer networks (SIPNs),wherein forming a polymer film includes dissolving the polymer in asolvent selected from alcohols, ketones, ethers, and combinationsthereof.
 15. The process according to claim 10, wherein forming astiffener includes: depositing an oxide on the top section of the firstsubstrate, wherein the stiffener has a roughness that greater than orequal to prime grade polish.
 16. The process according to claim 10,wherein delaminating the bottom section from the top section includes:heating under conditions to cause a first delamination stress in theembrittlement zone, wherein the first delamination stress is greaterthan a second delamination stress that exists between the polymer filmand the stiffener.
 17. The process according to claim 10, whereinforming a first oxide layer upon the fracture surface includes: forminga first dielectric layer on the fracture surface by a process selectedfrom thermal oxide growth, thermal nitride growth, thermal carbidegrowth, thermal oxide growth followed by carbon doping, oxide chemicalvapor deposition, nitride chemical vapor deposition, carbide chemicalvapor deposition, carbon-doped oxide chemical vapor deposition, andcombinations thereof.
 18. The process according to claim 10, beforecontacting the fracture surface with a dielectric layer on a thirdsubstrate further including: forming the dielectric layer on the thirdsubstrate, by a process selected from thermal oxide growth, thermalnitride growth, thermal carbide growth, thermal oxide growth followed bycarbon doping, oxide chemical vapor deposition, nitride chemical vapordeposition, carbide chemical vapor deposition, carbon-doped oxidechemical vapor deposition, and combinations thereof.
 19. The processaccording to claim 10, before contacting the fracture surface with adielectric layer on a third substrate further including: forming theoxide layer on the third substrate, wherein the dielectric layer on thethird substrate and the first dielectric layer are substantiallyidentical oxides selected from silica, alumina, ceria, thoria, zirconia,hafnia, titania, and combinations thereof.
 20. A process comprising:providing a first wafer including a top section and a bottom section anda stiffener disposed against the top section; providing an intermediatesubstrate including a first side and a second side and a polymer filmdisposed on the first side; applying the polymer film to the stiffener;treating the polymer film under conditions that cause the polymer toreflow against the stiffener and to outgas; and delaminating the bottomsection.
 21. The process according to claim 20, further including:debonding the polymer from the stiffener by a process selected fromlateral isotropic etching and wet isotropic etching through back-sideaccess through the intermediate substrate.
 22. The process according toclaim 20, further including: debonding the polymer from the stiffener bya process selected from lateral isotropic etching and isotropic etchingthrough back-side access through the intermediate substrate, wherein theetching is selected from a wet etch and a dry etch, and wherein the etchchemistry is selected from a wet etch and an oxygen plasma etch.
 23. Theprocess according to claim 20 following delaminating the bottom section,further including: forming a second top section and a second bottomsection in the bottom section; applying a second stiffener to the secondtop section; providing an intermediate substrate including a first sideand a second side and a polymer film disposed on the first side;applying the polymer film to the second stiffener; and delaminating thesecond bottom section.
 24. An article of manufacture comprising: a firstsubstrate active layer, wherein the first substrate active layerincludes an upper surface and a fracture surface that is disposedopposite the upper surface; a first dielectric layer disposed on thefracture surface; a stiffener disposed on the upper surface; a transfersubstrate disposed against the first dielectric layer, wherein thetransfer substrate includes a transfer substrate dielectric layer. 25.The article according to claim 24, wherein the stiffener has amicrosurface roughness that is greater than or equal to about 10 nm. 26.The article according to claim 24, wherein the first active substrateincludes a gate stack that extends into the stiffener.
 27. The articleaccording to claim 24, further including: a polymer film disposedagainst the stiffener, wherein the polymer film has a glass transitiontemperature above about 200° C.
 28. The article according to claim 24,further including: a polymer film disposed against the stiffener,wherein the polymer film is selected from poly(arylene ether) (PAE),poly(arylene ether ether ketone) (PAEEK), poly(arylene ether etheracetylene) (PAEEA), poly(arylene ether ether acetylene ether etherketone) (PAEEAEEK), poly(arylene ether ether acetylene ketone) (PAEEAK),poly(naphthylene ether) (PNE), and combinations thereof.
 29. The articleaccording to claim 24, wherein the first substrate active layer, thefirst dielectric layer, the stiffener, and the transfer substratecomprise a bonded, bottom silicon-film device and further including: abonded, upper silicon-film device disposed above the bonded, bottomsilicon-film device.
 30. The article according to claim 29, furtherincluding: at least one bonded silicon-film device disposed above thebonded, bottom silicon-film device, and wherein the upper silicon-filmdevice is disposed above the at least one bonded silicon-film device.